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TC530/TC534
5V Precision Data Acquisition Subsystems
Features
* Precision (up to 17-Bits) A/D Converter * 3-Wire Serial Port * Flexible: User Can Trade Off Conversion Speed For Resolution * Single Supply Operation * -5V Output Pin * 4 Input, Differential Analog MUX (TC534) * Automatic Input Polarity and Overrange Detection * Low Operating Current: 5mA Max * Wide Analog Input Range: 4.2V Max * Cost Effective
Package Types
28-Pin SOIC 28-Pin PDIP
VSS 1 CINT 2 CAZ 3 BUF 4 ACOM 5 CREF- 6 28 CAP27 AGND 26 CAP+ 25 VDD 24 NC
23 OSC TC530CPI CREF+ 7 TC530COI 22 VCCD VREF- 8 VREF+ 9 VIN- 10 VIN+ 11 DGND 12 N/C 13 OSCOUT 14 21 RESET 20 EOC 19 R/W 18 DIN 17 DCLK 16 DOUT 15 OSCIN
Applications
VSS 1
40-Pin PDIP
40 CAP39 AGND 38 CAP+ 37 VDD 36 N/C 35 N/C 34 OSC 33 N/C CINT 2 CAZ 3 BUF 4 ACOM 5 CREF- 6 CREF+ 7 VREF8 VREF+ 9
* Precision Analog Signal Processor * Precision Sensor Interface * High Accuracy DC Measurements
Device Selection Table
Part Number TC530COI TC530CPJ TC534CKW TC534CPL Package 28-Pin SOIC 28-Pin PDIP (Narrow) 44-Pin PQFP 40-Pin PDIP Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C
TC534CPL
32 VCCD 31 N/C 30 RESET 29 N/C 28 N/C 27 EOC 26 R/W 25 DIN 24 DCLK 23 DOUT 22 OSCIN 21 OSCOUT
CH4- 10 CH3- 11 CH2- 12 CH1- 13 CH4+ 14 CH3+ 15 CH2+ 16 CH1+ 17 DGND 18 A1 19 A0 20
44-Pin PQFP
AGND CAP+ CINT BUF CAPVDD CAZ VSS NC NC NC
44 43 42 41 40 39 38 37 36 35 34
NC ACOM CREFCREF+ VREFVREF+ CH4CH3CH2-
1 2 3 4 5 6 7 8 9
33 NC 32 OSC 31 NC 30 VCDD
TC534CKW
29
NC
28 RESET 27 NC 26 NC 25 NC 24 EOC 23 R/W
CH1- 10 CH4+ 11
12 13 14 15 16 17 18 19 20 21 22 OSCOUT OSCIN DOUT CH3+ CH2+ CH1+ DGND DCLK DIN A1 A0
2002 Microchip Technology Inc.
DS21433B-page 1
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TC530/TC534
General Description
The TC530/TC534 are serial analog data acquisition subsystems ideal for high precision measurements (up to 17-bits plus sign). The TC530 consists of a dual slope integrating A/D converter, negative power supply generator and 3 wire serial interface port. The TC534 is identical to the TC530, but adds a four channel differential input multiplexer. Key A/D converter operating parameters (Auto Zero and Integration time) are programmable, allowing the user to trade conversion time for resolution. Data conversion is initiated when the RESET input is brought low. After conversion, data is loaded into the output shift register and EOC is asserted, indicating new data is available. The converted data (plus Overrange and polarity bits) is held in the output shift register until read by the processor or until the next conversion is completed, allowing the user to access data at any time. The TC530/TC534 timebase can be derived from an external crystal of 2MHz (max) or from an external frequency source. The TC530/TC534 requires a single 5V power supply and features a -5V, 10mA output which can be used to supply negative bias to other components in the system.
Typical Application
VDD MCP1525 100k CREF .01F VDD BUF CAZ IN+ INDIF. MUX (TC534 Only) INT CREF+ CREFVREF+ VREF- ACOM 0.01F RESET EOC State Machine DC-TO-DC Converter Serial Port Oscillator (/ 4) R/W DIN DOUT DCLK Optional Power-On Reset Cap
+5V VDD (TC530 Only) VINVIN+ CH1+ CH1CH2+ CH2CH3+ CH3CH4+ CH4-
CINT RINT CAZ
Dual Slope A/D Converter CMPTR A VDD B
TC534 (Only)
TC530 TC534
A0 A1
OSC CAP+ CAP-
VSS
OSCIN
OSCOUT
Negative Supply Output
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DS21433B-page 2
2002 Microchip Technology Inc.
TC530/TC534
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
Supply Voltage ...................................................... +6V Analog Input Voltage (VIN+ or VIN-).............VDD to VSS Logic Input Voltage......... (V DD + 0.3V) to (GND - 0.3V) Ambient Operating Temperature Range: PDIP Package (C)................. 0C to +70C SOIC Package (C) ................ 0C to +70C PQFP Package (C) ............... 0C to +70C Storage Temperature Range .............. -65C to +150C
TC530/TC530A/TC534 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = VCCD, C AZ = CREF = 0.47F, unless otherwise specified. Symbol V DD VCCD PD IS ICCD Analog R ZSE ENL NL ZSTC SYE FSTC IIN VCMR VINT VIN VREF TD Note 1: 2: 3: 4: Resolution Zero Scale Error with Auto Zero Phase End Point Linearity Max. Deviation from Best Straight Line Fit Zero Scale Temperature Coefficient Rollover Error Full Scale Temperature Coefficient Input Current Common-Mode Voltage Range Integrator Output Swing Analog Input Signal Range Voltage Reference Range Zero Crossing Comparator Delay -- -- -- -- -- -- -- -- VSS + 1.5 VSS + 0.9 VSS + 1.5 VSS + 1 -- -- -- 0.015 0.008 -- .012 -- 6 -- -- -- -- 2.0 17 0.5 0.030 0.015 -- -- -- -- VDD - 1.5 VDD - 0.9 VDD -1.5 VDD - 1 -- -- -- -- -- -- -- -- -- VSS + 1.5 VSS + 0.9 VSS + 1.5 VDD + 1 -- -- 0.005 0.015 -- 1 .03 10 -- -- -- -- -- 3.0 17 0.012 0.045 -- 2 -- -- -- VDD - 1.5 VDD - 0.9 VDD - 1.5 VDD - 1 -- Bits % F.S. % F.S. Note 1 and Note 2 % F.S. Note 1 and Note 2 V/C % F.S. Note 3 ppm/ C pA V V V V sec Ext. VREF T.C. = 0ppm/C VIN = 0V Note 1 Parameter Min Analog Power Supply Voltage Digital Power Supply Voltage TC530/TC534 Total Power Dissipation Supply Current (VS + PIN ) Supply Current (VCCD PIN) 4.5 4.5 -- -- -- TA = +25C Typ 5.0 5.0 -- 1.8 -- Max 5.5 5.5 25 2.5 1.5 TA = 0C to +70C Min 4.5 4.5 -- -- -- Typ -- -- -- -- -- Max 5.5 5.5 -- 3.0 1.7 V V m mA mA FOSC = 1MHz VDD = VCCD = 5V Unit Test Conditions
Integrate time 66msec, Auto Zero time 66msec, VINT (pk) = 4V. End point linearity at 1/4, 1/2 3/4, F.S. after full scale adjustment. Rollover error is related to capacitor used for CINT. See Table 5-2, Recommended Capacitor for C INT. TC534 Only.
2002 Microchip Technology Inc.
DS21433B-page 3
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TC530/TC534
TC530/TC530A/TC534 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = VCCD, C AZ = CREF = 0.47F, unless otherwise specified. Symbol Parameter Min Serial Port Interface VIH VIL IIN VOL T R, T F FXTL FEXT TRS TRD TDRS TPWL TPWH TDR ROUT FCLK IOUT Input Logic HIGH Level Input Logic LOW Level Input Current (DI, DO, DCLK) Logic LOW Output Voltage (EOC) Rise and Fall Times (EOC, DI, DO) Crystal Frequency External Frequency on OSCIN Read Setup Time Read Delay Time DCLK to D OUT Delay DCLK LOW Pulse Width DCLK HIGH Pulse Width Data Ready Delay Output Resistance Oscillator Frequency VSS Output Current 2.5 -- -- -- -- -- -- 1 250 450 150 150 200 -- -- -- -- -- -- 0.2 -- -- -- -- -- -- -- -- -- 65 100 -- -- 0.8 10 0.3 250 2.0 4.0 -- -- -- -- -- -- 85 -- 10 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 -- -- 1 250 450 150 150 200 -- -- -- 100 -- 10 2.0 4.0 -- -- 0.8 -- 0.35 V V A V nsec MHz MHz sec nsec nsec nsec nsec nsec kHz mA IOUT = 10mA COSC = 0 IOUT = 250A CL = 10pF TA = +25C Typ Max TA = 0C to +70C Min Typ Max Unit Test Conditions
Multiplexer VIMMAX Maximum Input Voltage RDSON Note 1: 2: 3: 4: Drain/Source ON Resistance -2.5 -- -- 6 2.5 10 -2.5 -- -- -- 2.5 -- V k
Integrate time 66msec, Auto Zero time 66msec, VINT (pk) = 4V. End point linearity at 1/4, 1/2 3/4, F.S. after full scale adjustment. Rollover error is related to capacitor used for CINT. See Table 5-2, Recommended Capacitor for C INT. TC534 Only.
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DS21433B-page 4
2002 Microchip Technology Inc.
TC530/TC534
2.0 PIN DESCRIPTIONS
PIN FUNCTION TABLE
Pin Number (TC534) 40-Pin PDIP 1 Pin Number (TC534) Symbol 44-Pin PQFP 40 VSS Description
The descriptions of the pins are listed in Table 2-1
TABLE 2-1:
Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC 1 1
Analog output. Negative power supply converter output and reservoir capacitor connection. This output can be used to provide negative bias to other devices in the system. Analog output. Integrator capacitor connection and integrator output. Analog input. Auto Zero capacitor connection. Analog output. Integrator capacitor connection and voltage buffer output. Analog input. This pin is ground for all of the analog switches in the A/D converter. It is grounded for most applications. ACOM and the input common pin (VIN - or CHX-) should be within the common mode range, CMR. Analog Input. Reference cap negative connection. Analog Input. Reference cap positive connection. Analog Input. External voltage reference negative connection. Analog Input. External voltage reference positive connection. Analog Input. Multiplexer channel 4 negative differential Analog Input. Multiplexer channel 3 negative differential Analog Input. Multiplexer channel 2 negative differential Analog Input. Multiplexer channel 1 negative differential Analog Input. Multiplexer channel 4 positive differential Analog Input. Multiplexer channel 3 positive differential Analog Input. Multiplexer channel 2 positive differential Analog Input. Multiplexer channel 1 positive differential Analog Input. Negative differential analog voltage input. Analog Input. Positive differential analog voltage input. Analog Input. Ground connection for serial port circuit. Logic Level Input. Multiplexer address MSB. Logic Level Input. Multiplexer address LSB.
2 3 4 5
2 3 4 5
2 3 4 5
41 42 43 2
CINT CAZ BUF ACOM
6 7 8 9 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 10 11 12 Not Used Not Used 14
6 7 8 9 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 10 11 12 Not Used Not Used 14
6 7 8 9 10 11 12 13 14 15 16 17 Not Used Not Used 18 19 20 21
3 4 5 6 7 8 9 10 11 12 13 14 Not Used Not Used 15 16 17 18
CREFCREF+ VREFVREF+ CH4CH3CH2CH1CH4+ CH3+ CH2+ CH1+ VNVIN + DGND A1 A0
OSCOUT Analog Input. Timebase for state machine. This pin connects to one side of an AT-cut crystal having an effective series resistance of 100 (typ) and a parallel capacitance of 20pF. If an external frequency source is used to clock the TC530/TC534 this pin must be left floating. OSCIN Analog Input. This pin connects to the other side of the crystal described in OSCOUT above. The TC530/TC534 may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (Max). If an external frequency source is used, OSCOUT must be left floating. A maximum operating frequency of 2MHz (crystal) or 4MHz (external clock source) is permitted.
15
15
22
19
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DS21433B-page 5
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TC530/TC534
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number (TC534) 40-Pin PDIP 23 24 Pin Number (TC534) Symbol 44-Pin PQFP 20 21 DOUT DCLK Description Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC 16 17 16 17
Logic Level Output. Serial port data output pin. This pin is enabled only when R/W is high. Logic Input, Positive and Negative Edge Triggered. Serial port clock. When R/W is high, serial data is clocked out of the TC530/TC534A (on DOUT ) at each high-to-low transition of DCLK. A/D initialization data (LOAD VALUE) is clocked into the TC530/TC534 (on DIN ) at each low-to-high transition of DCLK. A maximum serial port DCLK frequency of 3MHz is permitted. Logic Level Input. Serial port input pin. The A/D converter integration time (TINT) and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. Logic Level Input. This pin must be brought low to perform a write to the serial port (e.g. initialize the A/D converter). The DOUT pin of the serial port is enabled only when this pin is high. Open Drain Output. End-of-Conversion (EOC) is asserted any time the TC530/TC534 is in the AZ phase of conversion. This occurs when either the TC530/TC534 initiates a normal AZ phase or when RESET is pulled high. EOC is returned high when the TC530/TC534 exits AZ. Since EOC is driven low immediately following completion of a conversion cycle, it can be used as a DATA READY processor interrupt. Logic Level Input. It is necessary to force the TC530/TC534 into the Auto Zero phase when power is initially applied. This is accomplished by momentarily taking RESET high. Using an I/O port line from the microprocessor or by applying an external system reset signal or by connecting a 0.01F capacitor from the RESET input to VDD. Conversions are performed continuously as long as RESET is low and conversion is halted when RESET is high. RESET may therefore be used in a complex system to momentarily suspend conversion (for example, while the address lines of an input multiplexer are changing state). In this case, RESET should be pulled high only when the EOC is LOW to avoid excessively long integrator discharge times which could result in erroneous conversion. (See Applications Section). Analog Input. Power supply connection for digital logic and serial port. Proper power-up sequencing is critical, see the Applications section. Input. The negative power supply converter normally runs at a frequency of 100kHz. This frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and V+DD. See Section 6.0, Typical Characteristics. Analog Input. Power supply connection for the A/D analog section and DC-DC converter. Proper power-up sequencing is critical, (See the Applications section).
18
18
25
22
DIN
19
19
26
23
R/W
20
20
27
24
EOC
21
21
30
28
RESET
22
22
32
30
VCCD
23
23
34
32
OSC
25
25
37
35
VDD
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DS21433B-page 6
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TC530/TC534
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number (TC534) 40-Pin PDIP 38 39 40 28, 29, 31, 33, 35, 36 Pin Number (TC534) Symbol 44-Pin PQFP 36 37 38 1, 25, 26, 27, 29, 31, 33, 34, 39, 44 CAP+ AGND CAPNC Description Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC 26 27 28 13, 24 26 27 28 13, 24
Analog Input. Storage capacitor positive connection for the DC/DC converter. Analog Input. Ground connection for DC/DC converter. Analog Input. Storage capacitor negative connection for the DC/DC converter. No connect. Do not connect any signal to these pins.
2002 Microchip Technology Inc.
DS21433B-page 7
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TC530/TC534
3.0
3.1
DETAILED DESCRIPTION
Dual Slope Integrating Converter
The TC530/TC534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the integrator output to cross 0V (deintegrating). The resulting count is read as conversion data. A simple mathematical expression that describes dual slope conversion is:
In addition to the two phases required for dual slope measurement (Integrate and De-integrate), the TC530/ TC534 performs two additional adjustments to minimize measurement error due to system offset voltages. The resulting four internal operations (conversion phases) performed each measurement cycle are: Auto Zero (AZ), Integrator Output Zero (IZ), Input Integrate (INT) and Reference De-integrate (DINT). The AZ and IZ phases compensate for system offset errors and the INT and DINT phases perform the actual A/D conversion.
FIGURE 3-1: EQUATION 3-1:
Integrate Voltage = De-integrate Voltage
INTEGRATING CONVERTER NORMAL MODE REJECTION
Normal Mode Rejection (dB)
30
T = Measurement Period
EQUATION 3-2:
0
from which:
EQUATION 3-3:
(V IN)
[
(T INT)
(RINT)(CINT)
]
= (VREF)
[
(TDEINT)
(RINT)(CINT)
And therefore:
EQUATION 3-4:
TDEINT VIN = VREF[ T INT where: VREF = Reference Voltage TINT = Integrate Time TDEINT = Reference Voltage De-integrate Time Inspection of Equation 3-4 shows dual slope converter accuracy is unrelated to integrating resistor and capacitor values, as long as they are stable throughout the measurement cycle. This measurement technique is inherently ratiometric (i.e., the ratio between the TINT and TDEINT times is equal to the ratio between VIN and VREF). Another inherent benefit is noise immunity. Input noise spikes are integrated, or averaged to zero, during the integration period. The integrating converter has a noise immunity with an attenuation rate of at least -20dB per decade. Interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. For this reason, the integration period of the converter is often established to reject 50/ 60Hz line noise. The ability to reject such noise is shown by the plot of Figure 3-1.
]
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DS21433B-page 8
1 R INTCINT
TINT
VIN(T)DT =
1 RINTCINT
TDEINT 0
VREF
20
10
]
0 0.1/T
1/T Input Frequency
10/T
3.2
Auto Zero Phase (AZ)
This phase compensates for errors due to buffer, integrator and comparator offset voltages. During this phase, an internal feedback loop forces a compensating error voltage on auto zero capacitor (CAZ). The duration of the AZ phase is programmable via the serial port (see Section 4.1.1, AZ and INT Phase Duration).
2002 Microchip Technology Inc.
TC530/TC534
FIGURE 3-2: SERIAL PORT TIMING
Read Timing R/W TRD EOC DIN DOUT TDRS DCLK Read Format R/W EOC TPWL DCLK TDLS TPWL TRS R/W TLS DIN TLDS TLDL Write Timing R/W Write Default Timing
DOUT
EOC OVR SGN MSB
LSB
DCLK
Write Format R/W
DOUT
MSB
LSB
DCLK For Polled vs Interrupt Operation and Write Value Modified Cycle Use TC520A Data Sheet (DS21431).
FIGURE 3-3:
A/D CONVERTER TIMING
Conversion Phase Data to Serial Port Transmit Register EOC AZ Updated Data Ready TDR INT DINT IZ AZ Updated Data Ready
3.3
Input Integrate Phase (INT)
In this phase, a current directly proportional to differential input voltage is sourced into integrating capacitor CINT. The amount of voltage stored on CINT at the end of the INT phase is directly proportional to the applied differential input voltage. Input signal polarity (sign bit) is determined at the end of this phase. Converter resolution and speed is a function of the duration of the INT phase, which is programmable by the user via the serial port (see Section 4.1.1, AZ and INT Phase Duration). The shorter the integration time, the faster the
speed of conversion (but the lower the resolution). Conversely, the longer the integration time, the greater the resolution (but at slower the speed of conversion).
2002 Microchip Technology Inc.
DS21433B-page 9
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TC530/TC534
3.4 Reference De-integrate Phase (DINT)
3. Calculate LOAD VALUE
This phase consists of measuring the time for the integrator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0V. The resulting timer data is stored in the output shift register as converted analog data.
EQUATION 4-2:
[LOAD VALUE]10 = 256 - (TINT)(FIN) 1024 FIN can be adjusted to a standard value during this step. The resulting base, -10 LOAD VALUE, must be converted to a hexadecimal number and then loaded into the serial port prior to initiating A/D conversion.
3.5
Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at zero volts when the AZ phase is entered so that only true system offset voltages will be compensated for. All internal converter timing is derived from the frequency source at OSC IN and OSCOUT. This frequency source must be either an externally provided clock signal or an external crystal. If an external clock is used, it must be connected to the OSCIN pin and the OSC OUT pin must remain floating. If a crystal is used, it must be connected between OSCIN and OSCOUT and be physically located as close to the OSCIN and OSC OUT pins as possible. In either case, the incoming clock frequency is divided by four, with the resulting clock serving as the internal TC530/TC534 timebase.
4.2
DINT and IZ Phase Timing
The duration of the DINT phase is a function of the amount of voltage stored on the integrator capacitor during INT and the value of VREF. The DINT phase is initiated immediately following INT and terminated when an integrator output zero crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX)/2).
4.3
System RESET
4.0
4.1
4.1.1
TYPICAL APPLICATIONS
Programming the TC530/TC534
AZ AND INT PHASE DURATION
The TC530/TC534 must be forced into the AZ state when power is first applied. A .01F capacitor connected from RESET to VDD (or external system reset logic signal) can be used to momentarily drive RESET high for a minimum of 100msec.
4.4
Design Example
These two phases have equal duration determined by the crystal (or external) frequency and the timer initialization byte (LOAD VALUE). Timing is selected as follows: 1. Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection. 2. Estimate Crystal Frequency Crystal frequencies as high as 2MHz are allowed. Crystal frequency is estimated using:
Figure 4-1 shows a typical TC534 interrupt-driven application. Timing and component values are calculated from equations and recommendations made in Section 3.1 and Section 4.1 of this document. The EOC connection to the processor INT input is for interrupt-driven applications only. (In polled systems, the EOC output is available on DOUT). Given: Required resolution:16-bits (65,536 counts.) Maximum: VIN 2V Power supply voltage: +5V 60hz system 1. 2. Pick Integration time (TINT): 66msec Estimate crystal frequency.
EQUATION 4-1:
2(R)/TINT where: R = Desired Converter Resolution (in counts) FIN = Input Frequency (in MHz) INT = Integration Time (in seconds)
EXAMPLE 4-1:
FIN = 2R/TINT = 2 x 65536/66 x 10-3 = 1.98MHz (use 2MHz) 3. Calculate LOAD VALUE
EXAMPLE 4-2:
LOAD VALUE = 256 - (T INT)(FIN)/1024 = [128]10 [128] 10 = 80 hex
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DS21433B-page 10
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TC530/TC534
4. Calculate RINT
4.6
1.
Circuit Design/Layout Considerations
Separate ground return paths should be used for the analog and digital circuitry. Use of ground planes and trace fill on analog circuit sections is highly recommended EXCEPT for in and around the integrator section and CREF, CAZ (C INT, CREF, C AZ, RINT). Stray capacitance between these nodes and ground appears in parallel with the components themselves and can affect measurement accuracy. Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur in the internal state machines. It is recommended that the digital supply, VCCD, be powered up first. One method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. See Figure 4-1, TC530/TC534 Typical Application. Decoupling capacitors, preferably a higher value electrolytic or tantulum in parallel with a small ceramic or tantalum, should be used liberally. This includes bypassing the supply connections of all active components and the voltage reference. Critical components should be chosen for stability and low noise. The use of a metal-film resistor for RINT and Polypropylene or Polyphenelyne Sulfide (PPS) capacitors for CINT, CAZ and CREF is highly recommended. The inputs and integrator section are very high impedance nodes. Leakage to or from these critical nodes can contribute measurement error. A guard-ring should be used to protect the integrator section from stray leakage. Circuit assemblies should be exceptionally clean to prevent the presence of contamination from assembly, handling or the cleaning itself. Minute conductive trace contaminates, easily ignored in most applications, can adversely affect the performance of high impedance circuits. The input and integrator sections should be made as compact and close to the TC53X as possible. Digital and other dynamic signal conductors should be kept as far from the TC53X's analog section as possible. The microcontroller or other host logic should be kept quiet during a measurement cycle. Background activities such as keypad scanning, display refreshing and power switching can introduce noise.
EXAMPLE 4-3:
RINT = VINMAX/20 = 2/20 = 100k 5. Calculate CINT for maximum (4V) integrator output swing:
EXAMPLE 4-4:
CINT = (TINT)(20 x 10-6 )/ (VS - 0.9) = (.066)(20 x 10-6)/(4.1) = .32F (use closest value: 0.33F) Note: 6. Microchip recommended capacitor: Evox-Rifa p/n: SMR5 334K50J03L 2.
Choose CREF and CAZ based on conversion rate:
EXAMPLE 4-5:
Conversions/sec = 1/(TAZ + TINT + 2TINT + 2msec) = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which CAZ = C REF = 0.22F (Table 5-1)
3.
4. Note: 7. Microchip recommended capacitor: Evox-Rifa p/n: SMR5 224K50J02L4
Calculate VREF. 5.
EXAMPLE 4-6:
VREF = (V S - 0.9) (C INT) (R INT) 2(TINT)
= (4.1) (0.33 x 1 -6) (105) / 2(.066) = 1.025V
6.
4.5
Power Supply Sequencing
Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur. See Section 4.6, Circuit Design/ Layout Considerations. Failing to insure a proper power-up sequence can cause spurious operation.
7.
2002 Microchip Technology Inc.
DS21433B-page 11
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TC530/TC534
FIGURE 4-1:
TC530/TC534 TYPICAL APPLICATION
+5V C1 .01F IN1+ IN1IN2+ IN2VCCD Analog Inputs IN3+ IN31F IN4+ IN4CAZ 0.22F CINT EOC R/W DOUT DIN DCLK RESET VCCD VDD (Optional) INT I/O I/O I/O I/O 100 10F +5V
VDD .01F
Processor
.01F
CIN 0.33F
TC534
OSCIN X1: 2MHz OSCOUT VSS DGND -5V 1F +5V R1 100k
CAZ BUF RINT 100k CREF 0.22F MUX Channel Control 1F CAPCREF+ CREFA0 A1 CAP+
R2 100k VREF+ (1.03V) VREFACOM
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DS21433B-page 12
2002 Microchip Technology Inc.
TC530/TC534
5.0 SELECTING COMPONENT VALUES FOR THE TC530/TC534
Calculate Integrating Resistor (RINT) The desired full scale input voltage and amplifier output current capability determine the value of R INT. The buffer and integrator amplifiers each have a full scale current of 20A. The value of RINT is therefore directly calculated as follows: It is critical that the integrating capacitor have a very low dielectric absorption. PPS capacitors are an example of one such dielectric. Table 5-2 summarizes various capacitors suitable for CINT.
1.
TABLE 5-2:
RECOMMENDED CAPACITOR FOR CINT
Suggested Part Number* SMR5 104K50J0IL SMR5 224K50J2L SMR5 334K50J03L4 SMR5 474K50J04L
Value (F) 0.1 0.22 0.33
EQUATION 5-1:
RINT = where: VIN(MAX) = Maximum Input Voltage (full count voltage) R INT = Integrating Resistor (in m) For loop stability, RINT should be 50k. 2. Select Reference (CREF) and Auto Zero (CAZ) Capacitors C REF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 5-1. Larger values for CAZ and C REF may also be used to limit rollover errors. VINMAX 20 m
Note:
0.47
*Manufactured by Evox-Rifa, Inc.
5.2
Calculate VREF
The reference de-integration voltage is calculated using the following equaton:
EQUATION 5-3:
VREF = (VS - 0.9) (CINT) (RINT) 2(RINT) V
5.3
Serial Port
TABLE 5-1:
Conversion Per Second >7 2 to 7 2 or less Note:
C REF AND CAZ SELECTION
Typical Value of C REF, C AZ (F) 0.1 0.22 0.47 Suggested* Part Number SMR5 104K50J0IL SMR5 224K50J2L SMR5 474K50J04L
Communication with the TC530/TC534 is accomplished over a 3 wire serial port. Data is clocked into DIN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK. R/W must be HIGH to read converted data from the serial port and LOW to write the LOAD VALUE to the TC530/TC534.
5.4
Data Read Cycle
*Manufactured by Evox-Rifa, Inc.
5.1
Calculate Integrating Capacitor (CINT)
The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e.,IVDD - 0.9VI or IVSS +0.9VI). Using the 20A buffer maximum output current, the value of the integrating capacitor is calculated using the following equation.
Data is shifted out of the serial port in the following order: End of Conversion (EOC), Overrange (OVR), Polarity (POL), conversion data (MSB first). When R/W is high, the state of the EOC bit can be polled by simply reading the state of DOUT. This allows the processor to determine if new data is available without connecting an additional wire to the EOC output pin (this is especially useful in a polled environment). See Figure 5-1.
FIGURE 5-1:
SERIAL PORT DATA READ CYCLE
R/W
EQUATION 5-2:
(TINT) (20 x 10 CINT = (V S - 0.9)
-6)
DCLK
F
DOUT EOC OVR POL MSB LSB
where: TINT = Integration Period VS = IVDD I CINT = Integrated Capacitor Value (F).
2002 Microchip Technology Inc.
DS21433B-page 13
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TC530/TC534
5.5 Load Value Write Cycle 5.6 Input Multiplexer (TC534 Only)
Following the power-up reset pulse, the LOAD VALUE (which sets the duration of AZ and INT) must next be transmitted to the serial port. To accomplish this, the processor monitors the state of EOC (which is available as a hardware output or at DOUT). R/W is taken low to initiate the write cycle only when EOC is low (during the AZ phase). (Failure to observe EOC low may cause an offset voltage to be developed across CINT, resulting in erroneous readings). The 8-bit LOAD VALUE data on DIN is clocked in by DCLK. The processor then terminates the write cycle by taking R/W high. (Data is transferred from the serial input shift register to the time base counter on the rising edge of R/W and data conversion is initiated). See Figure 5-2. A 4-input, differential multiplexer is included in the TC534. The states of channel address lines A0 and A1 determine which differential VIN pair is routed to the converter input. A0 is the least significant address bit (i.e., channel 1 is selected when A0 = 0 and A1 = 0). The multiplexer is designed to be operated in a differential mode. For single-ended inputs, the CHx- input for the channel under selection must be connected to the ground reference associated with the input signal.
FIGURE 5-2:
Timing Status Conversion Phase
TC530/TC534 INITIALIZATION AND LOAD VALUE WRITE CYCLE
Power-up RESET Undefined Write LOAD VALUE to Serial Port Converter in Normal Service
AZ
AZ R/W brought LOW during AZ for serial port write cycle
INT
DINT
IZ
AZ...
Continuous Conversions R/W = HIGH strobes LOAD VALUE into timebase and starts conversion
R/W
Converter held in AZ state due to RESET = 1
RESET
DCLK
DIN
1 1 MSB EOC
0011 LOAD VALUE
1
1 LSB
5.7
DC/DC Converter
An on-board, TC7660H-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. The charge pump develops a negative output voltage by moving charge from the power supply to the reservoir capacitor at VSS by way of the commutating capacitor connected to the CAP+ and CAP- inputs. The charge pump clock operates at a typical frequency of 100kHz. If lower quiescent current is desired, the charge pump clock can be slowed by connecting an external capacitor from the OSC pin to VDD. Reference typical characteristics curves.
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DS21433B-page 14
2002 Microchip Technology Inc.
TC530/TC534
6.0 TYPICAL CHARACTERISTICS
The graphs and tables following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range), and therefore outside the warranted range.
Output Voltage vs. Load Current
5 4 OUTPUT VOLTAGE (V) 3 2 1 0 -1 -2 -3 -4 -5 0 10 20 30 40 50 60 70 80 Slope 60
Output Voltage vs. Output Current
-0 -1 TA = 25C
OUTPUT VOLTAGE (V)
TA = 25C V+ = 5V
-2 -3 -4 -5 -6 -7 -8 0 2 4 6 8 10 12 14 16 18 20
LOAD CURRENT (mA)
OUTPUT CURRENT (mA)
Output Ripple vs. Load Current
OUTPUT SOURCE RESISTANCE ()
Output Source Resistance vs. Temperature
100 90 80 70 60 50 40 -50 -25 0 25 50 TEMPERATURE (C) 75 100 V+ = 5V IOUT = 10mA
200
OUTPUT RIPPLE (mV PK-PK)
175 150 125 100 75 50 25 0 0
V+ = 5V, TA = 25C Osc. Freq. = 100kHz CAP = 1F
CAP = 10F
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (mA)
Oscillator Frequency vs. Capacitance
100
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
Oscillator Frequency vs. Temperature
150 V+ = 5V
TA = +25C V+ = 5V
125
10
100
75
1 1 10 100 1000 OSCILLATOR CAPACITANCE (pF)
50 -50
-25
0
25 75 50 TEMPERATURE (C)
100
125
2002 Microchip Technology Inc.
DS21433B-page 15
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TC530/TC534
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
7.2
Taping Forms
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
28-Pin SOIC (W)
24 mm
12 mm
1000
13 in
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PQFP
24 mm
16 mm
500
13 in
NOTE: Drawing does not represent total number of pins.
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DS21433B-page 16
2002 Microchip Technology Inc.
TC530/TC534
7.3 Package Dimensions
28-Pin PDIP (Narrow)
PIN 1
.288 (7.32) .240 (6.10)
.045 (1.14) .030 (0.76) .310 (7.87) .290 (7.37)
1.400 (35.56) 1.345 (34.16) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92)
.040 (1.02) .015 (0.38)
.015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87)
3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
.022 (0.56) .015 (0.38)
Dimensions: inches (mm)
40-Pin PDIP (Wide)
PIN 1
.555 (14.10) .530 (13.46)
2.065 (52.45) 2.027 (51.49)
.610 (15.49) .590 (14.99)
.200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
2002 Microchip Technology Inc.
DS21433B-page 17
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TC530/TC534
7.3 Package Dimensions (Continued)
28-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65) .291 (7.40) .398 (10.10)
.713 (18.11) .697 (17.70) .103 (2.62) .097 (2.46) .019 (0.48) .014 (0.36) .012 (0.30) .004 (0.10)
8 MAX. .050 (1.27) .016 (0.40)
.013 (0.33) .009 (0.23)
Dimensions: inches (mm)
44-Pin PQFP
.009 (0.23) .005 (0.13)
7 MAX.
PIN 1 .018 (0.45) .012 (0.30)
.041 (1.03) .026 (0.65)
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.031 (0.80) TYP.
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX.
Dimensions: inches (mm)
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DS21433B-page 18
2002 Microchip Technology Inc.
TC530/534
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21433B-page 19
TC530/534
NOTES:
DS21433B-page 20
2002 Microchip Technology Inc.
TC530/TC534
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21433B-page 21
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04/20/02
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DS21433B-page 22
2002 Microchip Technology Inc.
*B33412SD*

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